To increase microprocessor performance, the number of circuit elements and clock frequencies used by microprocessors, often referred to as “CPUs”, have increased. Also, as the number of circuits in a CPU has increased, the number of parallel operations has risen. Examples of efforts to create more parallel operations include increased pipeline depth and an increase in the number of functional units in super-scalar and very-long-instruction-word architectures. As CPU performance continues to increase, the result has been a larger number of circuits switching at faster rates. Thus, from a design perspective, important considerations, such as the time needed to complete a simulation and the time needed to debug a CPU, must be taken into account.
As new CPU designs include more circuit elements, often operating at increased frequencies, the time required to simulate a CPU increases. Due to the increased time for simulation, the number of and breadth of tests, often referred to as “test coverage”, decreases. The result has been an increase in the number of logic errors that escape detection before the CPU is manufactured.
After a CPU prototype is initially manufactured and failure modes are uncovered, the time required to determine the failure mechanisms is generally increasing due to the increased CPU complexity. Failure modes may be the result of logic errors or poor manufacturability of one or more circuit elements. Circuit simulation helps determine the existence of a logic error. If a logic error does not exist, the manufacturability of a circuit element may be the root cause. Even after a failure mechanism is discovered and a solution is proposed, the time required to satisfactorily determine that the proposed solution fixes the error and does not generate any new errors has increased. Circuit simulation is key to the design and debug of increasingly complex and faster CPUs.
CPU simulation may be performed at a “switch level”. Switch level simulations typically include active circuit elements, for example transistors, and passive circuit elements that may include, for example, resistors, capacitors, and inductors. A switch level circuit simulator know in the art is SPICE, which is an acronym for Simulation Program with Integrated Circuit Emphasis. SPICE typically models each element using an equation or lookup table. SPICE can accurately model the voltage and/or current of each circuit element across time.
CPU simulation may also be performed at a “behavioral level”. Behavioral level simulations typically use a hardware description language (HDL) that determine the functionality of a single circuit element or group of circuit elements. A behavioral level simulation language known in the art is Verilog, which is a standard language published by the Institute of Electrical and Electronics Engineers, Piscataway, N.J. Verilog uses a high level programming language to describe the relationship between the input and output of one or more circuit elements. Verilog describes on what conditions the outputs should be modified and what effect the inputs have. Verilog programs may also be used for logic simulations at the “register transfer level” (RTL).
HDL languages, such as Verilog, are designed for the efficient representation of hardware designs. Verilog has support for handling signals of arbitrary widths; not only for defining and using an arbitrary width signal, but for treating any sub-field of such a signal as a signal in its own right.
HDL simulations may be event driven or cycle-based. Event driven simulations propagate a change in state from one set of circuit elements to another. Event driven simulators may record relative timing information of the change in state so that timing and functional correctness may be verified. Cycle-based HDL simulations also simulate a change in state from one set of circuit elements to another. Cycle-based HDL simulations, however, evaluate the state of the system once at the end of each clock cycle. While specific intra-cycle timing information is not available, simulation speed is improved. Discrete component evaluations and re-evaluations are typically unnecessary upon the occurrence of every event.
Cycle-based simulations operate by evaluating the state of the circuit elements on clock transitions. State information is maintained from one cycle to the next by a state device. One example of a state device is a flip-flop. A flip-flop modifies its output to equal its input on a clock transition, for example, a low to high clock transition. Flip-flops are often connected to combinatorial logic. The combinatorial logic modifies the output from several flip-flops and creates a new input into another flip-flop. This sequential arrangement of flip-flop to combinatorial logic to flip-flop allows computations to occur and be temporarily stored within a single clock cycle. This arrangement also allows multiple combinatorial logic blocks to operate in parallel.
The behavior of flip-flops coupled with combinatorial logic is ideal for cycle-based simulation because a change in state may only propagate to the next flip-flop. The flip-flop will propagate the change in state only on the next clock transition. Cycle-based simulation records a change in state only on a clock transition, which corresponds to the time a flip-flop modifies the state of the simulation.
In FIG. 1a, for example, flip-flops (52, 54) update their respective outputs (57, 59) with their respective inputs, IN 1 (51) and IN 2 (53), when a low to high transition occurs on CLK (55). This change is drawn in a timing diagram in FIG. 1b. Outputs (57, 59) are inputs to a combinatorial logic cone (56). The combinatorial logic cone (56) is representative of any combination of combinatorial logic elements. Combinatorial logic elements include, but are not limited to, any elements that provide Boolean logic functionality. The cone structure refers to an arrangement where more inputs exist than outputs, hence a “cone” structure. In this example, the combinatorial logic cone (56) may respond to one or both of the inputs. A combinatorial logic cone output (61) is designed to arrive at flip-flop (58) before the CLK (55) transitions from high to low. The high to low transition of CLK (55) causes flip-flop (58) to update flip-flop output OUT 3 (63) with the combinatorial logic cone output (61) as drawn in the timing diagram in FIG. 1b. 
A clock transition on which a change in the state of the system occurs is defined as a “phase”. In FIG. 1a, the low to high transition of CLK (55), is referred to as phase A. The high to low transition of CLK (55) is referred to as phase B. Any logical element that may change state due to the transition of an associated clock is referred to by the phase of the clock transition. For example, flip-flops (52, 54) and respective outputs (57, 59) change when CLK (55) transitions from low to high; therefore, they are classified as phase A. All inputs to combinatorial logic cone (56) are from phase A; therefore, the combinatorial logic cone output (61) is classified as phase A. Flip-flop (58) and output (63) change when CLK (55) transitions from high to low; therefore, they are classified as phase B.
The behavior of flip-flops is ideal for cycle-based simulation because a change in state may only occur on a clock transition. Other types of latches, for example a transparent latch, may change its output so long as a clock input signal to the transparent latch remains at an active level. Cycle-based simulators are not typically arranged to simulate a transparent latch.